Sigma-Delta (SD) Digital-to-Analog Converters (DAC) operate to convert digital signals into analog signals, FIG. 1 is a block diagram of an SD DAC 100, according to an example. As shown, the SD DAC 100 includes a digital input 102, a digital translator 104, an analog low-pass filter (LPF) 106, and a voltage output 108.
The digital translator 104 typically operates to adjust logic levels received on the digital input 102. For example, the digital translator 104 may convert logic “1” levels on the digital input 102 to an ideally precise positive reference voltage of +VR and convert logic “0” or “−1” levels to an ideally precise negative reference voltage of −VR, Relative to ground, the magnitude of −VR may be equal to the magnitude of +VR.
The adjusted logic level is then applied to the LPF 106. The LPF 106 may be of a given order (e.g., 1st order, 2nd order, or 3rd order) and usually includes a cut-off frequency, f0. As shown in FIG. 1, the output of the LPF 106 includes the voltage output 108. An average baseband component of the voltage output 108 may be described by the following equation:VOUT=2d(DIN)VR−VR In the above equation, “d” represents the density of ones or equivalent duty cycle of the digital input 102. Note that the voltage output 108 is equal to +VR when d equals “1”, equal to −VR when d equals “0”, and equal to zero when d equals “½”.
Generally, the bandwidth of the SD DAC 100 output signal includes a maximum frequency component, fMAX. Further, the digital input 102 to the SD DAC 100 may be clocked by a digital clock (or more than one digital clock) so that this data changes at a digital-clock frequency, or sampling signal frequency, of fS. The ratio of the digital sampling frequency, fS, to the Nyquist frequency of the highest frequency component of the analog output signal may be referred to as an oversampling ratio (OSR).
For proper operation of the SD DAC 100, certain frequency relationships must be maintained. For example, it is usually necessary for the cut-off frequency of the LPF, f0, to be greater than the maximum signal frequency, fMAX. Additionally, the cut-off frequency, f0, must usually be much less than the digital-clock frequency, fS, divided by the oversampling ratio, OSR. The following equation may describe the required relationships between the frequencies:fMAX<f0<<fS/(2*OSR)
The oversampling ratio, OSR, may provide an indication as to the accuracy of the SD DAC 100. The indication of the accuracy of the SD DAC 100 may also be expressed in terms of the number of binary or DAC bits, n, as ½n. The relationship between the cut-off frequency, f0, and the number of binary bits may be described by:f0<<fS/2(n+1) 
As the frequency margin between fS/2(n+1) and f0 increases, the SD DAC 100 operates more accurately. For example, fS/2(n+1) is typically several orders of magnitude greater than the cut-off frequency, f0, to minimize quantization noise during operation of the SD DAC 100. On the other hand, as the frequency margin between fS/2(n+1) and Co increases, the SD DAC 100 operates with less signal bandwidth, thus decreasing overall performance of the SD DAC 100. At times, it may be desirable to increase the signal bandwidth of the SD DAC 100, even though doing so decreases the frequency margin between fS/2(n+1) and f0.